Panelist: “An Evening of Innovation” Sponsored by Qualcomm
2022 IEEE ROBERT N. NOYCE MEDAL RECIPIENT
Jingsheng Jason Cong’s innovative contributions to electronic design automation (EDA) tools and field programable gate-array (FPGA) synthesis have enabled the efficient management of the exponential growth of design complexity of semiconductor chips that power our computation and communication infrastructures. FPGAs are semiconductor devices based on a matrix of configurable logic gates connected via programmable interconnects that can be reprogrammed to desired application requirements after manufacturing. As FPGAs grow in complexity to hundreds of millions of logic gates, it is essential to have EDA tools that can efficiently manage such complexity. Cong has made seminal contributions in three key areas of EDA tool development: logic synthesis algorithms for FPGAs, interconnect optimization algorithms for physical design, and high-level synthesis from programming languages friendly to software programmers. Cong’s research set the foundation of FPGA synthesis technology with a polynomial time-depth-optimal mapping algorithm for look-up-table-based FPGA designs that is now a cornerstone in all FPGA synthesis tools. His team further developed a number of highly innovative FPGA synthesis algorithms that enabled the efficient support of complex programmable logic blocks, embedded memories, and physical synthesis. Cong’s research then shifted emphasis to high-level synthesis (HLS). His group developed xPilot, a platform-based HLS system that is capable of generating high-quality designs with drastic reduction of design time and improvement in performance. His team made a number of algorithmic innovations in HLS, such as scheduling using systems of difference constraints, efficient pattern-mining based resource sharing, scheduling with soft constraints, behavior-level don’t-care analysis and optimization, and automatic memory partitioning. Cong is also a leader in customizable computing. He led the Customizable Domain-Specific Computing project in 2009 (funded by a U.S National Science Foundation Expeditions in Computing Award), which made an important shift from parallelization to customization using his HLS technology and demonstrated orders of magnitude performance and energy efficiency improvements in many application domains, including deep learning, medical imaging, and genomic sequencing analysis.
An IEEE Fellow and member of the U.S. National Academy of Engineering, Cong is the Valene Chair for Engineering Excellence with the Computer Science Department at the University of California, Los Angeles, Los Angeles, CA, USA.